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d a t a sh eet preliminary speci?cation file under integrated circuits, ic14 1996 jan 08 integrated circuits PCE84C882 microcontroller for monitor osd and auto-sync applications
1996 jan 08 2 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 contents 1 features 1.1 general 1.2 special 1.3 osd 2 general description 3 ordering information 4 block diagram 5 pinning information 5.1 pinning 5.2 pin description 6 reset 6.1 reset trip level 6.2 reset status 7 analog (dc) control 7.1 6 and 7-bit pwm outputs 7.2 14-bit pwm output 7.3 a typical pwm output application 8 analog-to-digital converter (adc) 8.1 conversion algorithm 8.2 typical adc application 9 on screen display (osd) 9.1 horizontal starting position control 9.2 vertical starting position control 9.3 vertical jumping cancelling 9.4 on-chip clock generator 10 display ram organization 10.1 description of display ram codes 10.2 default values of osd after power-on-reset 10.3 loading character data into display ram 10.4 writing character data into display ram 11 character rom 11.1 character rom address map 11.2 character rom organization 11.3 combination of character font cells 12 osd control registers 12.1 derivative register 22 12.2 derivative register 23 12.3 derivative register 33 12.4 derivative register 34 12.5 derivative register 35 12.6 derivative register 36 12.7 derivative register 37 13 to format the osd 13.1 number of characters per row 13.2 number of rows per frame 13.3 character size selection for different display resolutions 14 i 2 c-bus interface 15 8-bit counter (t3) 16 output ports 16.1 mask options 17 derivative registers 18 limiting values 19 dc characteristics 20 ac characteristics 21 development support 22 package outline 23 soldering 23.1 introduction 23.2 soldering by dipping or by wave 23.3 repairing soldered joints 24 definitions 25 life support applications 26 purchase of philips i 2 c components
1996 jan 08 3 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 1 features 1.1 general cmos 8-bit cpu (enhanced 8048 cpu) with 8 kbytes system rom and 192 bytes system ram one 8-bit timer/event counter (t1) and one 8-bit counter triggered by external input (t3) four single level vectored interrupt sources: external (intn), counter/timer, i 2 c-bus and vsyncn 2 directly testable inputs t0 and t1 on-chip oscillator clock frequency: 1 to 10 mhz on-chip power-on-reset with low power detector twelve quasi-bidirectional i/o lines, configuration of each i/o line individually selected by mask option idle and stop modes for reduced power consumption operating temperature: - 25 to +85 c operating voltage: 4.5 to 5.5 v package: sdip42. 1.2 special master-slave i 2 c-bus interface three 6-bit pulse width modulated outputs (pwm4; pwm6 and pwm7) four 7-bit pulse width modulated outputs (pwm0 to pwm3) one 14-bit pulse width modulated output (pwm8) one 4-bit adc channel 14 derivative i/o ports. 1.3 osd maximum dot frequency (f osd ): 20 mhz (see section 20 for details) display ram: 64 10 bits display character fonts: 62 + 2 special reserved codes character matrix: 12 18 (no spacing between characters) 4 character sizes: 1h/1v, 1h/2v, 1h/3v and 1h/4v 64 horizontal starting positions (4 dots for each step) 64 vertical starting positions (4 scan lines for each step) vertical jumping cancelling circuit spacing between character rows: 0, 4, 8 and 12 scan lines foreground colours: 8 on a character-by-character basis background colours: 8 on a word-by-word basis background/shadowing modes: 4 modes available, no background, north shadowing, box shadowing and frame shadowing (raster blanking) on a frame basis on-chip phase-locked loop (pll) oscillator (auto-sync with hsync) with programmable oscillator for on screen display (osd) function character blinking frequency: programmable using f vsync divisors of 16, 32, 64 and 128; on a frame basis character blinking ratios: 1 : 1, 1 : 3 and 3 : 1 programmable active level polarities of vsyncn, hsyncn, r, g, b and fb flexible display format by using carriage return code auto display ram address (dcrar) incremented after write operation to the character data register (dcrcr) vsyncn generates an interrupt (enabled by software) when vien is active. 2 general description the PCE84C882 is the enhanced version of the pce84c886 having all the features of this device but in addition provides: two dedicated power pins for the pll oscillator circuit a choice of two mask-programmable prescaler values for the pll oscillator a higher frequency osd clock - up to 20 mhz an improved edge-sensitive counter (t3). differences between the PCE84C882 and the pce84c886 are shown in table 1 and also highlighted throughout the document. the PCE84C882 is a member of the 84cxxx cmos microcontroller family. it is suitable for use with auto-sync monitors handling mode detection, digital and dpms control and has an enhanced osd facility for menu driving applications. the device uses the pce84cxx processor core and has 8 kbytes of rom and 192 bytes of ram. i/o requirements are catered for with 12 general purpose bidirectional i/o lines plus 14 derivative i/o lines. 8 pwm analog outputs are available for analog control purposes and one 4-bit adc. the device has an 8-bit counter, for use in pulse counting applications; an 8-bit timer/counter with programmable clock and an on-chip programmable pll oscillator that generates the osd clock. a master-slave i 2 c-bus interface and 2 directly testable lines are also available. the block diagram of the PCE84C882 is shown in fig.1.
1996 jan 08 4 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 table 1 differences between the PCE84C882 and the pce84c886 3 ordering information feature PCE84C882 pce84c886 maximum dot frequency (f osd ) 20 mhz 14 mhz maximum hsync frequency 90 khz 64 khz pll prescaler value 2 or 4 2 digital to analogue converter 1 channel 3 channels pulse width modulated outputs 8 channels 9 channels derivative i/o pins 14 16 counter t3 input edge sensitivity 0.4 m s1 m s pin assignment pin 21 v ssp v ss pin 22 c dp07/pwm7 pin 23 v ddp dp06/pwm6 pin 24 dp05 dp05/pwm5 pin 30 v ss test/emu pin 37 dp07/pwm7 dp11/adc1 pin 38 dp06/pwm6 dp10/adc0 pin 41 test/emu c type number package name description version PCE84C882 sdip42 plastic shrink dual in-line package; 42 leads (600 mil) sot270-1
1996 jan 08 5 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 4 block diagram fig.1 block diagram. (1) alternative function of dp0. (2) alternative function of dp1. (3) alternative function of dp2. handbook, full pagewidth pcf84cxx core excluding rom / ram 8-bit internal bus 8-bit timer / event counter cpu parallel i / o ports 8-bit counter rom 8 kbytes 3 x 6-bit pwm 4 x 7-bit pwm 4-bit adc i c-bus interface 2 on screen display 4 p0 v ss p1 dp0 dp1 dp2 pwm0 to pwm7 v ddp v ssp c fb vow0 vow2 vow1 vsyncn hsyncn v dd test / emu xtal1 (in) xtal2 (out) reset 14-bit pwm ram 192 bytes pwm8 adc2 sda scl mgc708 t1 intn / t0 t3 8-bit i / o ports 2 8 4 8 (1) (2) (2) (3) (3) (3) (3) pll oscillator
1996 jan 08 6 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 5 pinning information 5.1 pinning fig.2 pin configuration. handbook, halfpage mgc709 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 hsyncn vsyncn vow0/dp23 vow1/dp22 vow2 fb dp13/pwm8 p10 p11 p12 t3 p14 p00 p01 p02 p03 p04 p05 p06 p07 v ssp PCE84C882 test/emu dp20/sda dp21/scl dp06/pwm6 dp07/pwm7 dp12/adc2 intn/t0 t1 xtal2 (out) xtal1 (in) v ss dp01/pwm1 dp03/pwm3 v ddp dp00/pwm0 dp02/pwm2 dp04/pwm4 c dp05 dd v reset
1996 jan 08 7 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 5.2 pin description table 2 sdip42 package symbol pin description fb 1 video fast blanking output. vow2 2 video character output vow2. vow1/dp22 3 video character output vow1 or derivative port line dp22. vow0/dp23 4 video character output vow0 or derivative port line dp23. vsyncn 5 vertical synchronization signal input. hsyncn 6 horizontal synchronization signal input. p10 7 port line 10 or emulation input dxwr. p11 8 port line 11 or emulation input dxrd. dp13/pwm8 9 derivative i/o port or pwm8 output. p12 10 port line 12 or emulation input dxale. t3 11 secondary 8-bit counter input (schmitt trigger). p14 12 port line 14 or emulation output dxint. p00 to p07 13 to 20 general i/o port lines. v ssp 21 ground pin of pll circuit. c 22 external low-pass ?lter for on-chip pll osd oscillator. v ddp 23 power supply pin of pll circuit. dp00/pwm0 to dp07/pwm7 29, 28, 27, 26, 25, 24, 38, 37 derivative i/o ports or pwm outputs. note that dp05 has no derivative function. v ss 30 ground pin. xtal1 (in) 31 oscillator input pin for system clock. xtal2 (out) 32 oscillator output pin for system clock. reset 33 reset input; active low input initializes device. t1 34 direct testable pin or event counter input. intn/t0 35 external interrupt or direct testable pin. dp12/adc2 36 derivative i/o port or adc channel 2 input. dp21/scl 39 derivative port line or i 2 c-bus clock input. dp20/sda 40 derivative port line or i 2 c-bus data input. test/emu 41 control input for testing and emulation mode, normally low. v dd 42 power supply.
1996 jan 08 8 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 6 reset the reset pin may be used as an active low input to initialize the microcontroller to a defined state. an active reset can be generated by driving the reset pin from an external logic device. such an active reset pulse should not fall off before v dd has reached its f xtal -dependent minimum operating voltage. a power-on-reset can be generated using an external rc circuit. to avoid overload of the internal diode, an external diode should be added in parallel if c reset 3 2.2 m f. the rc circuit is shown in fig.3. 6.1 reset trip level the reset trip voltage level for the PCE84C882 is in the range 0.7 to 1.9 v. if any input (for example hsync) goes high before v dd is applied, latch-up may occur and in this situation the PCE84C882 cannot be reset. the cause and effect of latch-up is shown in fig.4. 6.2 reset status derivative registers reset status; see table 38 for details program counter 00h memory bank 0 register bank 0 stack pointer 00h all interrupts disabled timer/event counter 1 stopped and cleared timer pre-scaler modulo-32 (ps = 0) timer flag cleared serial i/o interface disabled (eso = 0) and in slave receiver mode idle and stop mode cleared. fig.3 external components for reset pin. handbook, halfpage v v pca84c8xx internal reset r c mlc259 dd ss reset reset reset ( 100 k w ) fig.4 the influence of an active high signal being applied before power-on-reset. handbook, halfpage v v PCE84C882 internal reset internal v r c mgc710 dd dd v dd ss v ss reset reset hsync hsyncn reset
1996 jan 08 9 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 7 analog (dc) control the PCE84C882 has eight pulse width modulated (pwm) outputs for analog control purposes e.g. brightness, contrast, h-shift, v-shift, h-width, v-size, e-w, r (or g or b) gain control etc. each pwm output generates a pulse pattern with a programmable duty cycle. the eight pwm outputs are specified below: 3 pwm outputs with 6-bit resolution (pwm4, 6 and 7) 4 pwm outputs with 7-bit resolution (pwm0 to pwm3) 1 pwm output with 14-bit resolution (pwm8). the 6 and 7-bit pwm outputs are described in section 7.1; the 14-bit pwm output is described in section 7.2 and a typical pwm output application is described in section 7.3. 7.1 6 and 7-bit pwm outputs pwm outputs pwm0 to pwm4, pwm6 and pwm7, share the same pins as derivative port lines dp00 to dp04, dp06 and dp07, respectively. selection of the pin function as either a pwm output or a derivative port line is achieved using the appropriate pwmne bit in register 21 (see table 38). the polarity of the pwm outputs is programmable and is selected by the p7lvl or the p6lvl bit in register 23 (see section 12.2). the state of the p7lvl bit determines the polarity of the 7-bit pwms; the state of the p6lvl bit determines the polarity of the 6-bit pwms. the duty cycle of each pwm output is dependent upon the programmable contents of its associated data latch (registers 10 to 17 respectively, register 15 is not used as there is no pwm5 output). as the clock frequency of each pwm circuit is 1 3 f xtal , the pulse width of the pulse generated can be calculated as shown below. where (pwmn) is the decimal value held in the data latch. the maximum repetition frequency (f pwm ) of the 6 and 7-bit pwm outputs is shown below. for the 6-bit pwm outputs: for the 7-bit pwm outputs: the block diagram for the 6 and 7-bit pwm outputs is shown in fig.5. pulse width 3 pwmn () f xtal ---------------------------------- = f pwm f xtal 192 --------- - = f pwm f xtal 384 --------- - = fig.5 block diagram for 6 and 7-bit pwms. handbook, full pagewidth mlc069 dp0x data i/o dp0x/pwmx 6 or 7-bit pwm data latch p6lvl/p7lvl internal data bus pwmne 6 or 7-bit dac pwm controller q q f xtal 3
1996 jan 08 10 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.6 typical non-inverted output pulse patterns for 6 or 7-bit pwm outputs. handbook, full pagewidth f 64 or 128 1 2 3 m m + 1 m + 2 64 or 128 1 00 01 m 63 or 127 decimal value pwm data latch mlc261 xtal 3
1996 jan 08 11 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 7.2 14-bit pwm output pwm8 shares the same pin as derivative port line dp13. selection of the pin function as either a pwm output or as a derivative port line is achieved using the pwm8e bit in register 22 (see section 12.1). the block diagram for the 14-bit pwm output is shown in fig.7 and comprises: two 7-bit latches: pwm8l (register 18) and pwm8h (register 19) 14-bit data latch (pwmreg) 14-bit counter coarse pulse controller fine pulse controller mixer. data is loaded into the 14-bit data latch (pwmreg) from the two 7-bit data latches (pwm8h and pwm8l) when either of these data latches is written to. the upper seven bits of pwmreg are used by the coarse pulse controller and determine the coarse pulse width; the lower seven bits are used by the fine pulse controller and determine in which subperiods fine pulses will be added. the outputs out1 and out2 of the coarse and fine pulse controllers are ored in the mixer to give the pwm8 output. the polarity of the pwm8 output is programmable and is selected by the p8lvl bit in register 23, this is described in section 12.2. as the 14-bit counter is clocked by 1 3 f xtal , the repetition times of the coarse and fine pulse controllers may be calculated as shown below. coarse controller repetition time: fine controller repetition time: figure 8 shows typical pwm8 outputs, with coarse adjustment only, for different values held in pwm8h. figure 9 shows typical pwm8 outputs, with coarse and fine adjustment, after the coarse and fine pulse controller outputs have been ored by the mixer. t sub 384 f xtal --------- - = t r 49152 f xtal ---------------- = 7.2.1 c oarse adjustment an active high pulse is generated in every subperiod; the pulse width being determined by the contents of pwm8h. the coarse output (out1) is low at the start of each subperiod and will remain low until the time has elapsed. the output will then go high and remain high until the start of the next subperiod. the coarse pulse width may be calculated as shown below. 7.2.2 f ine adjustment fine adjustment is achieved by generating an additional pulse in specific subperiods. the pulse is added at the start of the selected subperiod and has a pulse width of 3/f xtal . the contents of pwm8l determine in which subperiods a fine pulse will be added. it is the logic 0 state of the value held in pwm8l that actually selects the subperiods. when more than one bit is a logic 0 then the subperiods selected will be a combination of those subperiods specified in table 3. for example, if pwm8l = 111 1010 then this is a combination of: pwm8l = 111 1110: subperiod 64 and pwm8l = 111 1011: subperiods 16, 48, 80 and 112. pulses will be added in subperiods 16, 48, 64, 80 and 112. this example is illustrated in fig.10. when pwm8l holds 111 1111 fine adjustment is inhibited and the pwm8 output is determined only by the contents of pwm8h. table 3 additional pulse distribution pwm8l additional pulse in subperiod 111 111 0 64 111 11 0 1 32 and 96 111 1 0 11 16, 48, 80 and 112 111 0 111 8, 24, 40, 56, 72, 88, 104 and 120 11 0 1111 4, 12, 20, 28, 36, 44, 52...116 and 124 1 0 1 1111 2, 6, 10, 14, 18, 22, 26, 30...122 and 126 0 11 1111 1, 3, 5, 7, 9, 11, 13, 15, 17...125 and 127 3f xtal pwm8h 1 + () [] pulse duration 127 pwm8h C () 3 f xtal -------- =
1996 jan 08 12 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.7 14-bit pwm block diagram. handbook, full pagewidth pwm8l pwm8h pwmreg ?ove instruction ?ov instruction data load timing pulse coarse 7-bit pwm fine pulse generator out2 out1 mixer q q p8lvl 14-bit counter q14 to 8 q7 to 1 polarity control bit pwm8 output f = f tdac xtal mlc071 7 7 7 7 load internal data bus 3
1996 jan 08 13 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.8 non-inverted pwm8 output patterns - coarse adjustment only. handbook, full pagewidth 127 0 1 2 m m + 1 m + 2 127 0 1 00 01 m 127 decimal value pwm8h data latch mlc263 f xtal 3 fig.9 non-inverted pwm8 output patterns - coarse and fine adjustment. handbook, full pagewidth f 127 0 1 2 m m + 1 m + 2 127 0 1 00 01 m 127 decimal value pwm8h data latch mlc262 xtal 3
1996 jan 08 14 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.10 fine adjustment output (out2). handbook, full pagewidth mlc755 t sub0 t sub16 t sub32 t sub48 t sub64 t sub80 t sub96 t sub112 t sub127 t r 111 1110 111 1011 111 1010 pwm8l 7.3 a typical pwm output application a typical pwm application is shown in fig.11. the buffer is used to reduce jitter on the osd. r1 and c1 form the integration network the time constant of which should be at least 5 times greater than the repetition period of the pwm output pattern. in order to smooth a changing pwm output a high value of c1 should be chosen. the value of c1 will normally be in the range 1 to 10 m f. the potential divider chain formed by r2 and r3 is used only when the output voltage is to be offset. the output voltages for this application are calculated using equations (1) and (2). (1) (2) the loop from the pwm pin through r1 and c1 to v ss will radiate high frequency energy pulses. in order to limit the effect of this unwanted radiation source, the loop should be kept short and a high value of r1 selected. the value of r1 will normally be in the range 3.3 to 100 k w . it is good practice to avoid sharing v ss (pin 30) with the return leads of other sensitive signals. v max r3 supply voltage r3 r1 r2 r1 r2 + ---------------------- + ---------------------------------------------------- = v min r1 r3 r1 r3 + --------------------- - supply voltage r2 r1 r3 r1 r3 + ---------------------- + ------------------------------------------------------------------ - = fig.11 typical pwm output circuit. handbook, halfpage mgc711 c1 r3 r1 r2 PCE84C882 pwmn v ss supply voltage analog output
1996 jan 08 15 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 8 analog-to-digital converter (adc) the single channel adc comprises a 4-bit digital-to-analog converter (dac); a comparator; an analog channel selector and control circuitry. as the digital input to the 4-bit dac is loaded by software (a subroutine in the program), it is known as a software adc. the block diagram is shown in fig.12. the adc input adc2, shares the same pin as derivative port line dp12. selection of the pin function as either an adc input or as a derivative port line is achieved using bit adce2 in register 22. when adce2 = 1, the adc function is enabled (see section 12.1). the adc channel selector is controlled by the adcs1 and adcs0 bits in register 20. as the PCE84C882 provides only one adc channel, adcs1 bit must be set to a logic 1 and adcs0 bit must be set to a logic 0. all other settings are invalid. the 4-bit dac analog output voltage (v ref ) is determined by the decimal value of the data held in bits dac0 to dac3 of register 20. v ref is calculated as shown in equation (3) and table 4 lists the v ref values assuming v dd =5v. (3) when the analog input voltage is higher than v ref , the comp bit in register 20 will be high. table 4 selection of v ref dac3 dac2 dac1 dac0 v ref (v) 0000 0.3125 0001 0.6250 0010 0.9375 0011 1.2500 0100 1.5625 0101 1.8750 0110 2.1875 0111 2.5000 1000 2.8125 1001 3.1250 1010 3.4375 1011 3.7500 1100 4.0625 1101 4.3750 1110 4.6875 1111 5.0000 v ref v dd 16 ---------- dac value 1 + () = 8.1 conversion algorithm there are many algorithms available to achieve the adc conversion. the algorithm described below and shown in fig.13 uses an iteration process. 1. enable and then select the adc2 channel for conversion. channel selection is achieved using bits adcs1 and adcs0 in register 20. 2. set the digital input to the dac to 1000. the digital input to the dac is selected using bits dac3 to dac0 in register 20. 3. determine the result of the compare operation. this is achieved by reading the comp bit in register 20 using the instruction mov a, d20. if comp = 1; the analog input voltage is higher than the reference voltage (v ref ). if comp = 0; the analog input voltage is lower than the reference voltage (v ref ). 4. if comp = 1; then the analog input voltage is higher than the reference voltage (v ref ) and therefore the digital input to the dac needs to be increased. set the input to the dac to 1100. 5. if comp = 0; then the analog input voltage is lower than the reference voltage (v ref ) and therefore the digital input to the dac needs to be decreased. set the input to the dac to 0100. 6. determine the result of the compare operation by reading the comp bit in register 20. 7. for the dac = 1100 case if comp = 1; then the analog input voltage is still greater than v ref and therefore the digital input to the dac needs to be increased again. set the input to the dac to 1110. if comp = 0; then the analog input voltage is now less than v ref and therefore the digital input to the dac needs to be decreased. set the input to the dac to 1010 8. for the dac = 0100 case if comp = 1; then the analog input voltage is now greater than v ref and therefore the digital input to the dac needs to be increased. set the input to the dac to 0110. if comp = 0; then the analog input voltage is still lower than v ref and therefore the digital input to the dac needs to be decreased again. set the input to the dac to 0010.
1996 jan 08 16 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 9. the operations detailed in 6, 7 and 8 above are repeated and each time the digital input to the dac is changed accordingly; as dictated by the state of the comp bit. the complete process is shown in fig.13. each time the dac input is changed the number of values which the analog input can take is reduced by half. in this manner the actual analog value is honed into. the value of the analog input (v a ) is determined using equation (4): (4) as the conversion time of each compare operation is greater than 6 m s but less than 9 m s; a nop instruction is recommended to be used in between the instructions that change the value of v ref ; select the adc channel and read the comp bit. v a v dd 16 ---------- dac value 1 + () = fig.12 block diagram of 1 channel adc. h andbook, full pagewidth 4-bit dac comparator dac3 dac2 dac1 dac0 adce2 adcs1 adcs0 mgc712 adc enable selection dac value selection enable selector adc channel selector dp12/adc2 v ref en derivative port selector en2 ?ov a, d20? instruction to read comp bit comp bit internal bus channel selection - +
1996 jan 08 17 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 handbook, full pagewidth mlc073 value = 1000 comp = 1 tf value = 1100 comp = 1 tf value = 1110 comp = 1 tf value = 1111 comp = 1 value = 1101 comp = 1 tf 1111 1110 tf 1101 1100 value = 1010 comp = 1 tf value = 1011 comp = 1 value = 1001 comp = 1 tf 1010 tf 1001 1000 1011 value = 0100 comp = 1 tf value =0110 comp = 1 tf value = 0111 comp = 1 value = 0101 comp = 1 tf 0111 0110 tf 0101 0100 value = 0010 comp = 1 tf value = 0011 comp = 1 value = 0001 comp = 1 tf 0010 tf 0001 0011 0000 fig.13 example of converting algorithm for software adc.
1996 jan 08 18 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 8.2 typical adc application the adc2 channel of the PCE84C882 can be used in keypad applications to detect and identify the operation of individual keys. the circuit for a 14-key application is shown in fig.14. when no key is depressed the input voltage at the dp12/adc2 pin will be greater than 15 16 v dd and if the dac value selected is 1110 then the comp bit will be high. when any key is depressed the input voltage at the dp12/adc2 pin will change, and as each key will generate its own unique input voltage, this can be measured by the adc2 channel and the actual key depressed can then be identified. the input voltage generated by the operation of any key (ignoring the effect of the 100 k w resistor) can be calculated as follows: where n is the key number and can take any integer value in the range 1 to 14. the input voltage at the adc input will be influenced by the tolerance of the resistors and the length of the cable connecting the keypad to the monitor. in the worse case situation this may reduce the number of keys that can be uniquely detected and identified. v adcn n 0.5 C () 16 ------------------------ v dd = handbook, halfpage 5 k w key 14 dp12/adc2 v dd mgc718 PCE84C882 key 13 key 2 key 1 2 k w 2 k w 2 k w 1 k w 14 key matrix 100 k w v ss fig.14 a typical adc application for keypad detection.
1996 jan 08 19 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 9 on screen display (osd) the osd feature of the PCE84C882 enables the user to display information on the monitor screen. display information can be created using 62 customer designed characters, a space character and a carriage return code. the osd block diagram is shown in fig.15. 9.1 horizontal starting position control the horizontal starting position counter is incremented every osd clock after hsync becomes inactive and is reset when hsync becomes active. the horizontal starting position of the display row is determined by the contents of register 36; 1 of 64 positions may be selected as explained in section 12.6. the polarity of the active state of the hsyncn input is programmable and is determined by the hp bit in register 34; see section 12.4. the active high and active low states as selected by the hp bit are shown in fig.16. 9.2 vertical starting position control the vertical starting position counter is incremented every hsync cycle and is reset when vsync becomes active. the vertical starting position of the display row is determined by the contents of register 35; 1 of 64 positions may be selected as explained in section 12.5. to achieve the same starting position with different display resolutions, only the contents of register 35 need to be changed, the contents of register 36 remain the same. the lowest vertical starting position that can be selected, is located on the 256th scan-line. however, lower positions may be achieved using the carriage return code. when the selected horizontal and vertical starting positions are reached on screen; the osd is enabled. the character selected in display ram is then displayed. the polarity of the active state of the vsyncn input is programmable and is determined by the vp bit in register 34; see section 12.4. the active high and active low states as selected by the vp bit are shown in fig.16. 9.3 vertical jumping cancelling if the h-shift of the monitor is altered then vertical jumping of the osd may occur if the rising or falling edges of the hsync and vsync signals are too close. the PCE84C882 has on-chip vertical cancelling circuitry that prevents this from happening. 9.4 on-chip clock generator the on-chip oscillator generates an osd clock that is auto-sync with hsync. the frequency of the osd clock is programmable and is determined by the contents of the 7-bit counter (register 25) and also the prescaler value selected by mask option (a prescaler value of 2 or 4 can be selected). for 31 to 64 khz auto-sync monitors, a prescaler value of 4 is selected; for 31 to 90 khz auto-sync monitors a prescaler value of 2 or 4 can be selected. the osd clock frequency is calculated as follows: where (register 25) denotes the decimal value held in register 25. the block diagram of the osd clock is shown in fig.17. the internal reference frequency is connected to hsync, and if the frequency of hsync changes the output frequency (f osd ) will be changed linearly. the internal hsync signal is designed active high, consequently f pll is synchronized with the falling edge of this signal (end of back-tracing period). the osd clock is enabled/disabled by the state of the en bit in register 34; see section 12.4. when the osd clock is disabled the oscillator remains active, therefore the transient time from the osd clock start-up to locking into the external hsync signal is reduced. to ensure that the osd clock is stable and in-phase with hsync before the display is enabled, the end bit of the space code can be used to enable the osd feature; the procedure is as follows. 1. write a space code to address 00h of display ram, the end bit value is logic 1. 2. set the en bit in register 34 to logic 0. 3. write a space code to address 00h of display ram, the end bit value is logic 0. two dedicated power pins: v ddp and v ssp , isolate the oscillator supplies from other circuits thus reducing any radiated noise that might effect the voltage controlled oscillator. radiated noise is further reduced because as the oscillator is always active after power-on when the osd clock is enabled no large currents will flow (as in the case of rc or lc oscillators). f osd f hsync 2or4 () register 25 () =
1996 jan 08 20 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 handbook, full pagewidth mgc714 c 1 c pll oscillator polarity control hsyncn vsyncn internal synchronous circuit instruction decoder control register control signals horizontal position register/ counter character size control vertical position register/ counter counter write address address buffer selector display character ram display rom display control and output stage control register rgbfb vow1 vow0 vow2 fb cpu bus v ddp v ssp r 1 r 2 fig.15 osd block diagram.
1996 jan 08 21 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.16 hsyncn and vsyncn active level selection. handbook, full pagewidth mlc286 character display interval hsyncn/vsyncn pin hp/vp = 1 (active high) hsyncn/vsyncn pin hp/vp = 0 (active low) fig.17 block diagram for osd oscillator. handbook, full pagewidth mgc716 voltage controlled oscillator charge pump and loop filter phase/ frequency detector programmable 7-bit counter f osd 2 hsync (30 to 90 khz) osd disable f pll c mask option 2
1996 jan 08 22 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 10 display ram organization the display ram is organized as 64 10 bits. the general format of each ram location is as follows. bits <9-4> hold character data (62 customer designed character fonts plus two reserved codes). bits <3-0> contain the attributes of the character font, for example colour, character size, blinking etc. display ram is updated during the vertical back-tracing period (vsync will generate an interrupt when it becomes active). 10.1 description of display ram codes there are three data formats for display ram code: 1. character font code 2. carriage return code 3. space code. the three data formats are shown in tables 5, 6 and 7. table 5 format of character font code table 6 format of carriage return code table 7 format of space code 987654321 0 c5 c4 c3 c2 c1 c0 t3 t2 t1 t0 character font code (00h - 3dh) foreground colour blink 9876543210 c5 c4 c3 c2 c1 c0 t3 t2 t1 t0 carriage return code (3eh) character size line spacing 987654321 0 c5 c4 c3 c2 c1 c0 t3 t2 t1 t0 space code (3fh) background colour end
1996 jan 08 23 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 10.1.1 c haracter f ont c ode if bits <9-4> are in the range (00h to 3dh), then this is a character font code and 1 from 62 customer designed character fonts can be selected. bits <3-1> determine the colour of the character, a choice of 8 colours being available. bit <0> determines whether the character blinks or not. the blinking duty cycle and frequency are controlled by derivative register 33, see section 12.3. the format of the character font code is shown in table 5. table 8 selection of foreground colour table 9 selection of blinking function 10.1.2 c arriage r eturn c ode if bits <9-4> hold 3eh, then this is the carriage return code. the current display line is terminated (a transparent pattern appears on the screen) and the next character will be displayed at the beginning of the next line. bits <3-2> select the size of the of the character to be displayed on the next line. bits <1-0> determine the spacing between lines of displayed characters. spacing is a multiple of the number of horizontal scan lines. the format of the carriage return code is shown in table 6. t3 (red) t2 (green) t1 (blue) colour 0 0 0 black 0 0 1 blue 0 1 0 green 0 1 1 cyan 100red 1 0 1 magenta 1 1 0 yellow 1 1 1 white t0 blinking 0 off 1on table 10 selection of character size note 1. h is the osd clock period; v is the number of horizontal scan lines per dot. table 11 selection of line spacing 10.1.3 s pace c ode if bits <9-4> hold 3fh, then this is the space code. a transparent pattern, equal to one character width, will be displayed on the screen. bits <3-1> determine the background colour of the characters including the space code in box shadowing mode, but following the space code in north shadowing mode. see sections 12.4 and 12.3.1 for more details. background colour selection is the same as foreground colour selection. bit <0> is the end-of-display bit and indicates the end of display of the current screen before exhaustion of display ram (i.e. before the 64th ram location). the format of the space code is shown in table 7. table 12 end of display control t3 t2 character dot size (1) 0 0 1h/1v 0 1 1h/2v 1 0 1h/3v 1 1 1h/4v t1 t0 line spacing 0 0 0h line 0 1 4h line 1 0 8h line 1 1 12h line t0 display control 0 continue display of next character; this is also the default setting 1 end of display
1996 jan 08 24 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 10.2 default values of osd after power-on-reset frequency of osd clock: undefined, must be programmed background/shadowing mode: no background mode background/shadowing colour: blue character size: 1h/1v osd disabled full 64 display ram displayed (end of display bit = 0) vow1e and vow0e disabled horizontal starting position: 5th dot vertical starting position: 256th scan-line polarity of hsyncn: active low polarity of vsyncn: active low output polarities of fb, vow0 to vow2: active high blinking ratio: 3 : 1 blinking frequency: 1 128 f vsync frame background colour: blue. after a power-on-reset, the osd can be set-up as required by selecting the space code as the first character (address 0) and the carriage return code as the next character (address 1). this procedure allows the user to select the initial background colour; character size and inter-line spacing. 10.3 loading character data into display ram three derivative registers are used to address and load data into the display ram. these registers are described below. 10.3.1 dcr a ddress r egister (dcrar) this is derivative register 30 and holds the address of the location in display ram to which the data held in registers dcrtr and dcrcr will be written to. 1 of 64 locations can be addressed. bits 7 and 6 are reserved. the contents of this register are automatically incremented after each write operation to a ram address, and become zero on overflow. table 13 dcr address register (dcrar) 76543210 -- a5 a4 a3 a2 a1 a0 10.3.2 dcr a ttribute r egister (dcrtr) this is derivative register 31 and holds the character font attribute data. the data will be loaded into bits <3-0> of the location in ram pointed to by the contents of dcrar. bits 7 to 4 are reserved. table 14 dcr attribute register (dcrtr) 10.3.3 dcr c haracter r egister (dcrcr) this is derivative register 32 and holds the character data that will be loaded into bits <9-4> of the location in ram addressed by the contents of dcrar. bits 7 and 6 are reserved. table 15 dcr character register (dcrcr) 10.4 writing character data into display ram the procedure for writing character data into the display ram is as follows: 1. select the start address in display ram. the start address is stored in dcrar and can take any value between 0 and 63. 2. load the character attributes into dcrtr. if the attributes of a series of displayed characters are the same, only dcrcr needs to be updated. 3. load the character data into dcrcr. the character data will specify either a character font code, the carriage return code or the space code. this operation loads the selected ram location with the data held in registers dcrtr and dcrcr. the address held in dcrar is then incremented by 1 pointing to the next ram location in anticipation of the next operation. after a master reset the contents of dcrar, dcrtr and dcrcr are zero. 76543210 ---- t3 t2 t1 t0 76543210 -- c5 c4 c3 c2 c1 c0
1996 jan 08 25 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 11 character rom 64 character fonts may be held in rom; 62 customer selected character fonts plus the carriage return code and the space code. customer selected fonts are mask programmable. each character font is stored in a 12 19 dot matrix. however, only elements in rows 1 to 18 can be selected as visible dots on the screen. row 0 is only used for the combination of two characters in a vertical direction when north shadowing mode is selected. 11.1 character rom address map figure 18 shows the rom address map. addresses 3eh and 3fh hold the reserved codes for carriage return and space functions, respectively. addresses (00h to 3dh) hold the customer selected character font codes. 11.2 character rom organization rom is divided into two parts: rom1 and rom2. the organization of the bit patterns stored in rom 1 and rom 2 and also the file format to submit to philips for customized character sets is shown in fig.19. regarding fig.19 the following points should be noted. 1. row 0 of each font is reserved for vertical combination of two fonts. 2. binary 1 denotes visual dots. 3. rom1 and rom2 data files are in intel hex format on a byte basis. each byte is structured high nibble followed by low nibble. 4. the unused last byte of each font in rom1 must be filled with ffh. 5. the unused last 2 1 2 bytes in rom2 must be filled with the same data as held in the corresponding address in rom1. 6. the data bytes of the last 2 reserved fonts (carriage return and space codes) should be filled with 00h. 7. cs denotes checksum. a software package (osdgem) that assists in the design of character fonts on-screen and that also automatically generates the bit pattern hex files is available on request. the package is run under the ms-dos environment for ibm compatible pcs. 11.3 combination of character font cells two (or more) character font cells may be combined in a horizontal or vertical direction to create a new higher resolution pattern. the combination of two cells in a horizontal direction is straight forward and requires no special precautions to be taken. when combining character cells in this manner all 4 background/shadowing modes are available. an example of combining two character font cells in a horizontal direction is shown in fig.20. however, the combination of two character font cells in a vertical direction is more difficult and care must be taken; otherwise, the new pattern may be created with gaps in its shadowing. an example of a character pattern with gaps is shown in fig.21. providing the steps listed below are followed no problems with shadowing will occur. the line spacing between two rows of characters must be programmed to 0h. this procedure is explained in section 10.1.2. if the north shadowing mode is selected then when combining two character cells in a vertical direction row 0 must contain the same bit pattern as held in row 18 of the character directly above it. this is shown in fig.22. if north shadowing is not required then row 0 should contain all zeros. fig.18 rom address map. 0 61 (3dh) 62 (3eh) 63 (3fh) mask programmable font carriage return code space code reserved code mlc287
1996 jan 08 26 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.19 character font pattern stored in rom1 and rom2. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 column row lsb msb rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 rom2 rom1 0 0 0 2 2 0 3 f c 2 2 0 2 2 0 3 f f 0 0 1 5 5 2 0 0 c 0 3 0 0 0 0 2 2 0 3 f c 2 2 0 2 2 0 3 f f 0 0 1 5 5 2 0 0 c 0 3 0 rom1 rom2 3 f c 2 2 0 2 2 0 3 f c 2 2 0 0 0 1 5 5 3 0 0 6 0 5 8 3 f c 2 2 0 2 2 0 3 f c 2 2 0 0 0 1 5 5 3 0 0 6 0 5 8 rom1 : 1 0 0 0 0 0 0 0 00 00 22 fc 03 22 20 f2 3f 01 20 55 0c 00 03 : 1 0 0 0 1 0 0 0 < - - - - - - - - - data for font 2 - - - - - - - - - - 12 34 - - - > : 1 0 0 0 2 0 0 0 < - - - - - - - - - data for font 3 - - - - - - - - - - 56 78 - - - > rom2 : 1 0 0 0 0 0 0 0 fc 03 22 20 c2 3f 20 12 00 53 65 00 58 : 1 0 0 0 1 0 0 0 < - - - - - - - - - data for font 2 - - - - - - - - - - > : 1 0 0 0 2 0 0 0 < - - - - - - - - - data for font 3 - - - - - - - - - - > byte # __ __ __ __ __ __ __ __ __ __ __ __ __ __ 0 1 2 3 4 5 6 7 8 9 a b c d e f f f c s f f c s f f c s 5x 78 ff c s 00 03 ff c s 1x 34 ff c s mlc076 1110987 6543210
1996 jan 08 27 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.20 combination of two character cells to form new font (in horizontal direction). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (a) character designed in character rom 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 mlb402 (b) north shadowing background mode display on screen
1996 jan 08 28 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.21 combination of two character fonts in a vertical direction - with gap. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cell boundary 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 18 if row 0 of the lower character does not contain the bit pattern of row 18 of the upper character in north shadowing mode, a gap in the shadow might occur mlb403 character pattern displayed on the screen character pattern stored in character rom
1996 jan 08 29 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.22 combination of two character fonts in a vertical direction - without gap. handbook, full pagewidth 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 cell boundary 01234567891011 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 01234567891011 18 row 0 of the lower character should contain the bit pattern of row 18 of the upper character in north shadowing mode to avoid a "break" in the shadow mlb404 character pattern displayed on the screen character pattern stored in the character rom
1996 jan 08 30 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 12 osd control registers the functions of the osd are controlled by derivative registers 22, 23, 33, 34, 35, 36 and 37. an overview of the function of each register is given in table 16. a full description of each register is given in sections 12.1 to 12.7. table 16 osd control registers overview register name register number address (hex) function con1 derivative register 22 22 this register is used to enable pwm8; the i 2 c-bus lines; the adc channel and the vow0 and vow1 lines. con2 derivative register 23 23 this register selects the output polarity of the pwm outputs and also enables and selects the vsyncn interrupt. con3 derivative register 33 33 this register selects the blinking frequency and the active ratio of the blinking frequency for the osd. con4 derivative register 34 34 this register selects the 4 display modes; the active state of hsyncn and vsyncn inputs and the output polarity of the fb and vow0 to vow2 outputs. it also enables/disables the osd clock. vpos derivative register 35 35 this register selects the vertical starting position of the display row. hpos derivative register 36 36 this register selects the horizontal starting position of the display row. frc derivative register 37 37 this register selects the background colour in frame shadowing mode.
1996 jan 08 31 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 12.1 derivative register 22 this register is used to enable pwm8; the i 2 c-bus lines; the adc2 input and the vow0 and vow1 lines. table 17 derivative register 22 table 18 description of derivative register 22 bits 76543210 pwm8e scle sdae adc2e adc1e adc0e vow1e vow0e bit symbol description 7 pwm8e pulse width modulated output pwm8 enable bit. when pwm8e = 1; pin 9 is selected as an output for pwm8. when pwm8e = 0; pin 9 is selected as derivative port line dp13 and the pwm function is disabled. 6 scle i 2 c-bus clock enable bit. when scle = 1; pin 39 is selected as the i 2 c-bus clock line. when scle = 0; pin 39 is selected as derivative port line dp21 and the i 2 c-bus function is disabled. 5 sdae i 2 c-bus data enable bit. when sdae = 1; pin 40 is selected as the i 2 c-bus data line. when sdae = 0; pin 40 is selected as derivative port line dp20 and the i 2 c-bus function is disabled. 4 adc2e adc channel 2 enable bit. the state of this bit determines whether pin 36 functions as an adc input or as derivative port line. when adc2e = 1; adc channel 2 is enabled. when adc2e = 0; derivative port line dp12 is enabled. 3 adc1e as the PCE84C882 has only one adc channel, these channel select bits are not used and both must be set to a logic 1. 2 adc0e 1 vow1e vow1e enable bit, when vow1e = 1; pin 3 is selected as the vow1 output. when vow1e = 0; pin 3 is selected as derivative port line dp22 and the vow function is disabled. 0 vow0e vow0e enable bit, when vow0e = 1; pin 4 is selected as the vow0 output. when vow0e = 0; pin 4 is selected as derivative port line dp23 and the vow function is disabled.
1996 jan 08 32 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 12.2 derivative register 23 this register selects the output polarity of the pwm outputs and also enables and selects the vsyncn interrupt. table 19 derivative register 23 table 20 description of derivative register 23 bits 76543210 vint vien --- p8lvl p7lvl p6lvl bit symbol description 7 vint vsyncn/sio interrupt indication bit. this bit indicates which of the two possible interrupt sources, the vsync signal (at the vsyncn pin) or the sio, generated the interrupt. the interrupt causes the program to jump to the i 2 c interrupt subroutine at address 05h. if vint = 1; then the interrupt was generated by vsync. if vint = 0; then the i 2 c-bus generated the interrupt. this bit must be reset after the interrupt has been serviced, otherwise additional unwanted interrupts will be generated. 6 vien vsyncn interrupt enable bit. when the sio interrupt is enabled and vien = 1; the vsync signal (at the vsyncn pin) will generate an interrupt to the cpu. the vsyncn interrupt is edge-triggered and can be selected to become active, using the vp bit in register 34, on the rising or falling edge of the vsync signal. in order to generate a vsyncn interrupt at the start of the vertical back tracing period, the vp bit must be set correctly; see section 12.4. the vsyncn interrupt and the i 2 c-bus interrupt share the same interrupt vector. 5 - these three bits are reserved. 4 - 3 - 2 p8lvl polarity select bit for output pwm8. when p8lvl = 0; the pwm8 output is not inverted. when p8vl = 1; the pwm8 output is inverted. 1 p7lvl polarity select bit for outputs pwm0 to pwm3. when p7lvl = 0; the pwm outputs are not inverted. when p8lvl = 1; the pwm outputs are inverted. 0 p6lvl polarity select bit for outputs pwm4 to pwm7. when p6lvl = 0; the pwm outputs are not inverted. when p6lvl = 1; the pwm outputs are inverted.
1996 jan 08 33 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 12.3 derivative register 33 derivative register 33 controls the character blinking functions. table 21 derivative register 33 table 22 description of derivative register 33 bits table 23 selection of blinking active ratio table 24 selection of blinking frequency 76543210 ---- br1 br0 bf1 bf0 bit symbol description 7 - these 4 bits are reserved. 6 - 5 - 4 - 3 br1 blinking active ratio select bits. these two bits allow one from a choice of three active blinking ratios to be selected; see table 23. 2 br0 1 bf1 blinking frequency select bits. these two bits allow one from a choice of four blinking frequencies to be selected; see table 24. 0 bf0 br1 br0 active ratio 0 0 3 : 1; this is also the default setting. 0 1 1:1 1 0 1:3 1 1 reserved bf1 bf0 blinking frequency (hz) 00 01 10 11 ; this is also the default setting. f vsync 16 ------------- - f vsync 32 ------------- - f vsync 64 ------------- - f vsync 128 ---------------
1996 jan 08 34 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 12.3.1 t he display of s pace and c arriage r eturn c haracters in the 4 display modes figures 23 to 26 show the display of space and carriage return characters in the 4 display modes, with the blinking function on and off. mode 0: no background mode. both the space code and the carriage return code are displayed as transparent (no bit) patterns, with the video signal as the background. this is shown in fig.23. mode 1: north shadowing mode. both codes are displayed in the same manner as for mode 0. this is shown in fig.24. in mode 2: box shadowing mode. the space code is displayed as a transparent pattern with selected background colour. this will also be the background colour of the character following the space code. however, when the space code is used as an end bit, it will be displayed as a transparent pattern superimposed on the video (see fig.30). the carriage return code in mode 2 is also displayed as a transparent pattern superimposed on the video signal. mode 3: frame shadowing mode. the space code and the carriage return code are both displayed as transparent patterns with background colour (see fig.26). fig.23 blinking in no background (superimpose) mode. mlb397 character on character off cr code sp code cr code sp code fig.24 blinking in north shadowing mode. mlb398 character on character off cr code sp code cr code sp code
1996 jan 08 35 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.25 blinking in box shadowing mode. mlb399 character on character off cr code cr code sp code sp code fig.26 blinking in frame shadowing mode. mlb401 character on character off cr code sp code cr code sp code
1996 jan 08 36 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 12.4 derivative register 34 this register selects the 4 display modes; the active state of signal at the hsyncn and vsyncn inputs and the output polarity of the fb and vow0 to vow2 outputs. it also enables/disables the osd clock. table 25 derivative register 34 table 26 description of derivative register 34 bits table 27 selection of display modes 76543210 -- s1 s0 hp vp bp en bit symbol description 7 - these two bits are reserved. 6 - 5 s1 display mode select bits; see table 27. 4s0 3 hp hsyncn signal polarity control bit. when hp = 0, the active level of the signal at the hsyncn input is low; this is also the default state. when hp = 1, the active level of the signal at the hsyncn input is high. see fig.16. 2 vp vsyncn signal polarity control bit. when vp = 0, the active level of the signal at the vsyncn input is low; this is also the default state. when vp = 1, the active level of the signal at the vsyncn input is high. see fig.16. 1 bp output polarity control bit for fb, vow0, vow1 and vow2. when bp = 1; these outputs are active high; this is also the default state. when bp = 0; these outputs are active low. 0 en osd clock enable/disable bit. when en = 1; the osd clock is enabled. when en = 0; the osd clock is disabled. s1 s0 display mode 0 0 mode 0: no background (superimpose) mode. the osd characters are superimposed on the monitor video signals. see fig.27. 0 1 mode 1: north shadowing mode. the characters shadows are generated as if a light source was placed north of the character (see fig.28). character shadowing only appears within the cell boundary. consequently, if row 18 contains a bit pattern then north shadowing will not be shown on the screen (see fig.20). the depth of shadow displayed is dependent upon the character size; characters with sizes of 1h/1v; 1h/2v and 1h/3v have a depth of shadow equivalent to 1 scan line whereas a character of size 1h/4v has a depth of shadow equivalent to 2 scan lines. examples of characters with north shadowing, for the 4 character sizes, are shown in fig.29. 1 0 mode 2: box shadowing mode. a background dot matrix of 12 18 bits surrounds the character font; where there is no foreground dot a background dot is displayed (see fig.30). 1 1 mode 3: frame shadowing mode. a background colour ?lls the whole screen when no bit patterns are being displayed (see fig.31). 1 of 8 background colours can be selected using derivative register 37; the default background colour is blue.
1996 jan 08 37 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.27 mode 0: no background (superimpose) mode. handbook, full pagewidth mos "m" : red + blue "o" : blue "s" : red + green fb sp code sp code r g b mlc077 scan line sp code
1996 jan 08 38 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.28 mode 1: north shadowing background mode. handbook, full pagewidth fb r g b 1st character : green 2nd character : blue character background shadowing : red mlc078 scan line
1996 jan 08 39 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.29 example of north shadowing mode. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 (a) character designed in character rom mlb396 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (b) 1h/2v or 1h/4v character displayed on the screen 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (c) 1h/1v character displayed on the screen 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (d) 1h/3v character displayed on the screen
1996 jan 08 40 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.30 mode 2: box shadowing (background) mode. handbook, full pagewidth "m" : foreground - red + blue background - green "o" : foreground - blue background - red "s" : foreground - red + green background - blue fb sp code (end) r g b mlc079 scan line m os sp code sp code
1996 jan 08 41 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.31 mode 3: frame shadowing mode. handbook, full pagewidth "m" : red + blue "o" : blue "s" : red + green frame background : green fb sp code r g b mlc080 scan line mos sp code sp code
1996 jan 08 42 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 12.5 derivative register 35 derivative register 35 selects the vertical starting position of the display row. table 28 derivative register 35 table 29 description of derivative register 35 bits. 12.6 derivative register 36 derivative register 36 selects the horizontal starting position of the display row. table 30 derivative register 36 table 31 description of derivative register 36 bits 76543210 -- v5 v4 v3 v2 v1 v0 bit symbol description 7 - these 2 bits are reserved. 6 - 5 v5 these 6 bits enable 1 of 64 vertical start positions to be selected for the display row. the vertical starting position is calculated as follows: where (v5 ? v0) is the decimal value of the contents of register 35; (v5 ? v0) 3 0. 4v4 3v3 2v2 1v1 0v0 76543210 -- h5 h4 h3 h2 h1 h0 bit symbol description 7 - these 2 bits are reserved. 6 - 5 h5 these 6 bits enable 1 of 64 horizontal start positions to be selected for the display row. the horizontal starting position is calculated as follows: where (h5 ? h0) is the decimal value of the contents of register 36; (h5 ? h0) 3 2. 4h4 3h3 2h2 1h1 0h0 vp 4 v5 v0 ? () [] horizontal scan lines = hp 4 h5 h0 ? () 5 + [] osd clock =
1996 jan 08 43 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 12.7 derivative register 37 derivative register 37 selects the background colour when the osd is in frame shadowing mode. table 32 derivative register 37 table 33 description of derivative register 37 bits table 34 selection of background colour 76543210 ----- frr frg frb bit symbol description 7 - these 5 bits are reserved. 6 - 5 - 4 - 3 - 2 frr these three bits are used to select the background colour in frame shadowing mode; see table 34. the default colour is blue. 1 frg 0 frb frr (red) frg (green) frb (blue) colour 0 0 0 black 0 0 1 blue 0 1 0 green 0 1 1 cyan 100red 1 0 1 magenta 1 1 0 yellow 1 1 1 white
1996 jan 08 44 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 13 to format the osd 13.1 number of characters per row the number of characters per row is a function of character width. the width of the character displayed is only dependent upon the value held in the 7-bit programmable counter (pllcn) and is not affected by a change in horizontal resolution (any change in f hsync will be reflected by a linear change in the frequency of the osd clock). the maximum number of characters per row can be determined by calculating the number of osd clock pulses that occur during the hsync active period and dividing the result by the number of horizontal dots in the character matrix (which is 12). if hsync is assumed to be active for 85% of its cycle period then the maximum number of characters per row (n) can be calculated as follows: 13.2 number of rows per frame the number of rows per frame is a function of character height and the spacing between the rows of characters. the height of a character displayed on the screen is determined by the number of visible scan lines per frame and the character size. the number of scan lines is dependent upon the resolution of the monitor; character size is selected by the user (see section 10.1.2). the PCE84C882 also provides a choice of four inter-line spaces: 0h, 4h, 8h and 12h (see section 10.1.2). if the inter-line spacing is assumed to be zero then the number of rows per frame (r) can be calculated by dividing the number of visible scan lines (sl) by the character size (cs) and dividing the result by the number of vertical dots in the character matrix (which is 18). this can be expressed mathematically as follows: table 35 shows the number of rows per frame for different horizontal resolutions. n 0.85 f osd 12 f hsync ----------------------------- = r sl 18 cs -------------------- - = 13.3 character size selection for different display resolutions to cater for the variable display resolutions (i.e. 640 x 400, 640 480, 800 600, 1024 768 and 1 280 1 024) of auto-sync monitors, the PCE84C882 offers a choice of 4 different character sizes: 1h/1v, 1h/2v, 1h/3v and 1h/4v. this allows the height of displayed characters to be of similar size even when the monitors resolution is changed (see table 35). table 35 recommended character size selection for different display resolutions 14 i 2 c-bus interface the PCE84C882 has an on-chip i 2 c-bus interface that can be used in master or slave mode. full details of the i 2 c-bus are given in the document the i 2 c-bus and how to use it . this document may be ordered using the code 9398 393 40011. the i 2 c-bus interface lines sda and scl share the same pins as derivative port lines dp20 and dp21 respectively. selection of the pin function as either an i 2 c-bus line or a derivative port line is achieved using the sdae and scle bits in derivative register 22 (see section 12.1). only port option 2 is available for both of these pins. resolution character size rows/frame 640 400 1h/2v 11 640 480 1h/3v 13 800 600 1h/3v 11 1024 768 1h/4v 10 1280 1024 1h/4v 14
1996 jan 08 45 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 15 8-bit counter (t3) one application for this counter is in the frequency measurement of the hsync signal. the block diagram of the 8-bit counter is shown in fig.33. a schmitt trigger is used at the input for noise rejection and also to shape the input signal into a square wave. the t3 input is sampled at a frequency of 1 3 f osc by the sample clock which synchronizes the internal t3 clock and the read operation of derivative register 24. the rising edge of the input increments the ripple counter by 1. the contents of t3 may be read using the instruction mov a, d24 (where d24 is derivative register 24). as soon as the data is read, the counter is reset to zero. a counter overflow or power-on-reset also resets the counter contents to zero. if the rising and falling edges of the input pulse are less than 30 ns then the minimum pulse width that the t3 input will recognise is 3/f osc + 100 ns. if the system clock is 10 mhz then the minimum pulse width is 400 ns. in some display modes, the active pulse width of the hsync signal can be less than 400 ns. in this situation, extra hardware circuitry may be necessary. handbook, halfpage t h t l 0.9 v dd 0.1 v dd 0.1 v dd 0.9 v dd t r t r t f mgc719 t f fig.32 t3 input waveform. fig.33 block diagram of the 8-bit counter (t3). handbook, full pagewidth mgc717 t3 power-on-reset sample clock read d24h emu 8-bit counter reset q0 to q7 ck data bus synchronisation circuit t3 counter control circuit
1996 jan 08 46 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 16 output ports each i/o port line may be individually configured using one of three mask options. the three i/o mask options are specified below: option 1 standard input/output with switched pull-up current source; this is shown in fig.34. option 2 input/output with open drain output; this is shown in fig.35. option 3 push-pull output; this is shown in fig.36. the state of each output port after a power-on-reset can also be selected using the mask options. all port mask options are given in section 16.1. fig.34 standard i/o with pull-up transistor source (option 1). handbook, full pagewidth mla696 tr3 i/o port line slave d sq sq master d mq write pulse outl/orl/anl/mov data bus orl/anl/mov in/mov tr1 v ss tr2 v dd constant current source 100 m a typ.
1996 jan 08 47 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 fig.35 open-drain i/o without pull-up transistor (option 2). handbook, full pagewidth mla697 i/o port line slave d sq sq master d mq write pulse outl/orl/anl data bus orl/anl in tr1 v ss v dd fig.36 push-pull output with pull-up transistor (option 3). handbook, full pagewidth mlb998 output line slave d sq sq master d mq write pulse outl / orl / anl data bus orl / anl in tr1 v ss tr2 v dd constant current source 100 m a typ.
1996 jan 08 48 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 16.1 mask options table 36 lists the port mask options for the PCE84C882. table 37 is intended for customer use when ordering the device. table 36 port options port pin option configuration reset state p00 13 1, 2 or 3 high or low p01 14 1, 2 or 3 high or low p02 15 1, 2 or 3 high or low p03 16 1, 2 or 3 high or low p04 17 1, 2 or 3 high or low p05 18 1, 2 or 3 high or low p06 19 1, 2 or 3 high or low p07 20 1, 2 or 3 high or low p10 7 1, 2 or 3 high or low p11 8 1, 2 or 3 high or low p12 10 1, 2 or 3 high or low p14 12 1, 2 or 3 high or low dp00 29 1, 2 or 3 high or low dp01 28 1, 2 or 3 high or low dp02 27 1, 2 or 3 high or low dp03 26 1, 2 or 3 high or low dp04 25 1, 2 or 3 high or low dp05 24 1, 2 or 3 high or low dp06 38 1, 2 or 3 high or low dp07 37 1, 2 or 3 high or low dp12 36 1, 2 or 3 high or low dp13 9 1, 2 or 3 high or low dp20 40 2 high dp21 39 2 high dp22 3 1, 2 or 3 high or low dp23 4 1, 2 or 3 high or low fb 1 2 or 3 high or low vow2 2 2 or 3 high or low table 37 customer selected mask options port pin option configuration reset state p00 13 p01 14 p02 15 p03 16 p04 17 p05 18 p06 19 p07 20 p10 7 p11 8 p12 10 p14 12 dp00 29 dp01 28 dp02 27 dp03 26 dp04 25 dp05 24 dp06 38 dp07 37 dp12 36 dp13 9 dp20 40 2 s dp21 39 2 s dp22 3 dp23 4 fb 1 vow2 2
1996 jan 08 49 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 17 derivative registers the PCE84C882 has 29 derivative registers. the derivative port i/o registers are located at addresses 00 to 05h. when dp0tr, dp1tr and dp2tr are read the data is read directly from the pin. however, when dp0r, dp1r and dp2r are read the data is read from the port latch (see figs 34 to 36 for the port configuration). as the PCE84C882 has no pwm5 output the corresponding enable bit (pwm5e) in the pwme register (address 21h) must be set to a logic 0. as the PCE84C882 has only one adc channel the channel select bits (adcs1 and adcs0) in the adccn register (address 20h) and the pin function enable bits (adce1 and adce0) in the con1 register (address 22h) must be set to the values specified in chapter 8. table 38 register map (see note 1) addr (hex) reg 7 6 5 4 3 2 1 0 r/w 00 dp0tr dp07 (x) dp06 (x) dp05 (x) dp04 (x) dp03 (x) dp02 (x) dp01 (x) dp00 (x) r 01 dp1tr - (x) - (x) - (x) - (x) dp13 (x) dp12 (x) -- r 02 dp2tr - (x) - (x) - (x) - (x) dp23 (x) dp22 (x) dp21 (x) dp20 (x) r 03 dp0r dp07 (1) dp06 (1) dp05 (1) dp04 (1) dp03 (1) dp02 (1) dp01 (1) dp00 (1) rw 04 dp1r - (x) - (x) - (x) - (x) dp13 (1) dp12 (1) dp11 (1) dp10 (1) rw 05 dp2r - (x) - (x) - (x) - (x) dp23 (1) dp22 (1) dp21 (1) dp20 (1) rw 10 pwm0 - (x) pwm06 (0) pwm05 (0) pwm04 (0) pwm03 (0) pwm02 (0) pwm01 (0) pwm00 (0) rw 11 pwm1 - (x) pwm16 (0) pwm15 (0) pwm14 (0) pwm13 (0) pwm12 (0) pwm11 (0) pwm10 (0) rw 12 pwm2 - (x) pwm26 (0) pwm25 (0) pwm24 (0) pwm23 (0) pwm22 (0) pwm21 (0) pwm20 (0) rw 13 pwm3 - (x) pwm36 (0) pwm35 (0) pwm34 (0) pwm33 (0) pwm32 (0) pwm31 (0) pwm30 (0) rw 14 pwm4 - (x) - (x) pwm45 (0) pwm44 (0) pwm43 (0) pwm42 (0) pwm41 (0) pwm40 (0) rw 16 pwm6 - (x) - (x) pwm65 (0) pwm64 (0) pwm63 (0) pwm62 (0) pwm61 (0) pwm60 (0) rw 17 pwm7 - (x) - (x) pwm75 (0) pwm74 (0) pwm73 (0) pwm72 (0) pwm71 (0) pwm70 (0) rw 18 pwm8l - (x) pwm86l (0) pwm85l (0) pwm84l (0) pwm83l (0) pwm82l (0) pwm81l (0) pwm80l (0) rw 19 pwm8h - (x) pwm86h (0) pwm85h (0) pwm84h (0) pwm83h (0) pwm82h (0) pwm81h (0) pwm80h (0) rw 20 adccn - (x) adcs1 (0) adcs0 (0) dac3 (0) dac2 (0) dac1 (0) dac0 (0) comp (2) (0) rw
1996 jan 08 50 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 notes 1. values within parethesis show the bit state after a reset operation. x denotes an undefined state. 2. this bit is read only. 18 limiting values in accordance with the absolute maximum rating system (iec 34) 21 pwme pwm7e (0) pwm6e (0) pwm5e (0) pwm4e (0) pwm3e (0) pwm2e (0) pwm1e (0) pwm0e (0) rw 22 con1 pwm8e (0) scle (0) sdae (0) adce2 (0) adce1 (0) adce0 (0) vow1e (0) vow0e (0) rw 23 con2 vint (0) vien (0) - (x) - (x) - (x) p8lvl (0) p7lvl (0) p6lvl (0) rw 24 t3con t3b7 (0) t3b6 (0) t3b5 (0) t3b4 (0) t3b3 (0) t3b2 (0) t3b1 (0) t3b0 (0) r 25 pllcn - (x) pll6 (0) pll5 (0) pll4 (0) pll3 (0) pll2 (0) pll1 (0) pll0 (0) rw 30 dcrar - (x) - (x) dcra5 (0) dcra4 (0) dcra3 (0) dcra2 (0) dcra1 (0) dcra0 (0) rw 31 dcrtr - (x) - (x) - (x) - (x) dcrt3 (1) dcrt2 (1) dcrt1 (1) dcrt0 (1) w 32 dcrcr - (x) - (x) dcrc5 (1) dcrc4 (1) dcrc3 (1) dcrc2 (1) dcrc1 (1) dcrc0 (1) w 33 con3 - (x) - (x) - (x) - (x) br1 (0) br0 (0) bf1 (1) bf0 (1) rw 34 con4 - (x) - (x) s1 (0) s0 (0) hp (0) vp (0) bp (1) en (0) rw 35 vpos - (x) - (x) v5 (1) v4 (1) v3 (1) v2 (1) v1 (1) v0 (1) w 36 hpos - (x) - (x) h5 (0) h4 (0) h3 (0) h2 (0) h1 (0) h0 (0) w 37 frc - (x) - (x) - (x) - (x) - (x) frr (0) frg (0) frb (1) w symbol parameter min. max. unit v dd supply voltage - 0.3 +8.0 v v i input voltage on any pin with respect to ground (v ss ) - 0.3 v dd + 0.3 v i oh maximum source current for all port lines -- 10.0 ma i ol maximum sink current for all port lines - 30.0 ma p tot total power dissipation - 1w t amb operating ambient temperature - 25 +85 c t stg storage temperature - 55 +125 c addr (hex) reg 7 6 5 4 3 2 1 0 r/w
1996 jan 08 51 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 19 dc characteristics v dd =5v 10% ;v ss =0v;t amb = - 25 to +85 c; all voltages with respect to v ss ; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v dd operating supply voltage 4.5 5.0 5.5 v i dd operating supply current f osd = f xtal = 10 mhz - 510ma f osd = f xtal = 6 mhz - 3.5 7 ma f osd = stop; f xtal =10mhz - 36 ma f osd = stop; f xtal = 6 mhz - 1.5 4 ma i lu latch-up current for all pins 50 -- ma v por power-on-reset voltage level 0.7 1.3 1.9 v ports p0, p1, dp0, dp1 and dp2 inputs v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i li input leakage current v ss < v i < v dd -- 10 m a port p0 outputs v ol low level output voltage v dd =5v; i ol =10ma -- 1.2 v i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v - 3.0 - 7.0 - ma dp00/pwm0 to dp07/pwm7 as derivative ports i ol low level output sink current v dd =5v; v ol = 0.4 v 5.0 12.0 - ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v - 3.0 - 7.0 - ma dp00/pwm0 to dp07/pwm7 as pwm outputs i ol low level output sink current v dd =5v; v ol = 0.4 v 0.7 1.5 - ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v - 0.7 - 1.5 - ma p10 to p12 and p14 outputs i ol low level output sink current v dd =5v; v ol = 0.4 v 5.0 12.0 - ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v - 3.0 - 7.0 - ma dp20/sda and dp21/scl outputs i ol low level output sink current v dd =5v; v ol = 0.4 v 3.0 -- ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v -- 7.0 - ma
1996 jan 08 52 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 vow1/dp22; vow0/dp23 and dp13/pwm8 as derivative output ports i ol low level output sink current v dd =5v; v ol = 0.4 v 5.0 12.0 - ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v - 3.0 - 7.0 - ma vow1/dp22 and vow0/dp23 as vow outputs i ol low level output sink current v dd =5v; v ol = 0.4 v 1.4 3.0 - ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5 v; v o =v dd - 0.4 v - 1.4 - 3.0 - ma dp13/pwm8 as pwm8 output i ol low level output sink current v dd =5v; v ol = 0.4 v 1.4 3.0 - ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v - 1.4 - 3.0 - ma outputs fb and vow2 i ol low level output sink current v dd =5v; v ol = 0.4 v 1.4 3.0 - ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v - 1.4 - 3.0 - ma dp12/adc2 as derivative output port i ol low level output sink current v dd =5v; v ol = 0.4 v 5.0 12.0 - ma i oh1 high level pull-up output source current v dd =5v; v o = 0.7v dd - 40 - 100 -m a v dd =5v; v o =v ss -- 140 - 400 m a i oh2 high level push-pull output source current v dd =5v; v o =v dd - 0.4 v - 3.0 - 7.0 - ma test/emu; reset; intn/t0; t1; hsyncn; vsyncn and t3 v il low level input voltage 0 - 0.3v dd v v ih high level input voltage 0.7v dd - v dd v i li input leakage current v ss < v i < v dd - 1.0 - +1.0 m a symbol parameter conditions min. typ. max. unit
1996 jan 08 53 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 20 ac characteristics symbol parameter conditions min. typ. max. unit f xtal crystal oscillator frequency v dd = 5 v; t amb = - 25 to +85 c option 1: g m = 0.4 ms 1 - 6 mhz option 2: g m = 1.2 ms 4 - 10 mhz f pxe pxe resonator frequency option 2: g m = 1.2 ms 1 - 5 mhz f osd osd clock frequency v dd = 4.75 v; t amb = +70 c 6.0 - 20 mhz f hsync hsync frequency duty cycle = 10 : 90 30 - 90 khz f vsync vsync frequency duty cycle = 10 : 90 50 - 120 hz c osd external capacitance at pin c - 0.33 -m f c xtal1 external capacitance at xtal1 (in) pin (pxe resonator) - 30 100 pf c xtal2 external capacitance at xtal2 (out) pin (pxe resonator) - 30 100 pf t t3 minimum pulse width period at t3 input rising or falling edge of t3 pulse < 30 ns 0.4 -- m s analog-to-digital (software) converter v ai adc2 comparator analog input voltage v ss - v dd v v ae conversion error range -- 1 2 lsb t afc conversion time (from any change in adc input i.e. voltage level or enable/disable) -- 7 m s
1996 jan 08 54 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 21 development support table 39 details the hardware items available for development support and table 40 lists the development support documentation. table 39 hardware table 40 documentation item type order number lcds development system mother board - lcds84 om1025 9339 931 50112 daughter board - lcd84c882 om4835 9350 861 10112 piggy-back version pca84c882b - 9350 872 50112 document name report number om4873 demo-board using PCE84C882 osd microcontroller in auto-sync monitor application an94049
1996 jan 08 55 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 22 package outline unit b 1 cee m h l references outline version european projection issue date iec jedec eiaj mm dimensions (mm are the original dimensions) sot270-1 90-02-13 95-02-04 b max. w m e e 1 1.3 0.8 0.53 0.40 0.32 0.23 38.9 38.4 14.0 13.7 3.2 2.9 0.18 1.778 15.24 15.80 15.24 17.15 15.90 1.73 5.08 0.51 4.0 m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 42 1 22 21 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) d (1) z a max. 12 a min. a max. sdip42: plastic shrink dual in-line package; 42 leads (600 mil) sot270-1
1996 jan 08 56 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 23 soldering 23.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 23.2 soldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 23.3 repairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds.
1996 jan 08 57 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 24 definitions 25 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 26 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 jan 08 58 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 notes
1996 jan 08 59 philips semiconductors preliminary speci?cation microcontroller for monitor osd and auto-sync applications PCE84C882 notes
philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40-2783749, fax. (31)40-2788399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil, p.o. box 7383 (01064-970), tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. (852)2319 7888, fax. (852)2319 7700 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (45)32 88 26 36, fax. (45)31 57 19 49 finland: sinikalliontie 3, fin-02630 espoo, tel. (358)0-615 800, fax. (358)0-61580 920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: p.o. box 10 51 40, 20035 hamburg, tel. (040)23 53 60, fax. (040)23 53 63 00 greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, bombay 400 018 tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)7640 000, fax. (01)7640 200 italy: philips semiconductors s.r.l., piazza iv novembre 3, 20124 milano, tel. (0039)2 6752 2531, fax. (0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5130, fax. (03)3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)709-1412, fax. (02)709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. (040)2783749, fax. (040)2788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (63) 2 816 6380, fax. (63) 2 817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494 spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (886) 2 382 4443, fax. (886) 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (66) 2 745-4090, fax. (66) 2 398-0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. 380-44-4760297, fax. 380-44-4766991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-2724825 scds47 ? philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 453061/1100/01/pp60 date of release: 1996 jan 08 document order number: 9397 750 00552

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